Neurotech Alliance

Probes

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Silicon Neural Nanoprobes

Quick Overview of Current Designs (Gen-2) 

Here we provide a quick synopsis of the probe designs for the current generation of nanoprobes. Complete design documents for all nanoprobe foundry runs are provided at the bottom of this web page, under the heading "Design Documents".

Figure 1.  Gen-2 Neural Nanoprobe Designs. Nanoprobes P01, P02, P04, P06, P07, P08, and P10 enable highly-multiplexed Ephys measurements. Nanoprobe P05 facilitates concurrent Echem and Ephys measurements. Specification for each of these probes is summarized in Table 1, below.

Figure 1.  Gen-2 Neural Nanoprobe Designs. Nanoprobes P01, P02, P04, P06, P07, P08, and P10 enable highly-multiplexed Ephys measurements. Nanoprobe P05 facilitates concurrent Echem and Ephys measurements. Specification for each of these probes is summarized in Table 1, below.

Table 1. Specifications for Gen-2 Ephys and Echem nanoprobes. For design P05, section 3.2 refers to the Gen-2 design document, which is linked below.

Table 1. Specifications for Gen-2 Ephys and Echem nanoprobes. For design P05, section 3.2 refers to the Gen-2 design document, which is linked below.

Figure 2.  Details of Ephys / Echem Nanoprobe Topography. Magenta regions comprise multiplexed nanowire runs from individual electrodes to their respective contacts at the probe head.

Figure 2.  Details of Ephys / Echem Nanoprobe Topography. Magenta regions comprise multiplexed nanowire runs from individual electrodes to their respective contacts at the probe head.


 

Design Documents

These documents provide an overview of the production runs and elucidate design details for probe architectures that have been foundry fabricated en masse.

Current Generation   (expected delivery ~Q4/2017):

Gen-2 (2016-2017) = Ephys & Echem (~12.6 MB)

Previous Generation(s)   (not available for dissemination):

Gen-1 (2014-2015) = Ephys (~8.4 MB)

Reference: Rios et al., Nano Lett (2016)

 

Readouts

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Overview of Ephys / Echem Data Acquisition Architecture

Our Gen-2 Ephys / Echem data acquisition system is shown below in Figure 1. It is compatible with from one to four 256-channel probe layers (as described on our Probes web page) ­ permitting assembly of instrumentation with either 256, 512, 768, or 1,024 full-time / full-bandwidth recording and stimulation channels. Each of our individual 256-channel probe layers are independently connected to the headstage via separate flexi-cables. These flexi-cables permit arbitrary and stress-free positioning of nanoprobes within the brain, untethered from the skull. They also permit experimentally-dependent scaling of probe-layer count, ranging from one to four probe layers in this generation. Our single-chip, custom 1,024-channel headstage ASIC (application specific integrated circuit) is mounted on the headstage board. The back end of the headstage board is connected by a cable to the controller board ­ which provides system control signals, stimulation protocols, and enables streaming Ephys data to a PC through USB-3 connections. Data acquisition and system control software have been coded for both Linux OS and Mac OS X. These components are summarized in Figure 1 below.

Figure 1. Ephys system building blocks that are being disseminated to the user community. Provided components constitute a complete measurement system, including: silicon neural nanoprobe; flexi-cable that connects probe to headstage electronics; the headstage board itself, containing our custom 1024-channel ASIC; the back-end controller board with USB-3 output; first-gen graphical user interface software for controlling system and acquiring data (Mac and PC compatible). The ribbon cable picture between the headstage and the controller boards will, in practice, be replaced with a fine wire bundle to permit free behavior of the subject under study.

Figure 1. Ephys system building blocks that are being disseminated to the user community. Provided components constitute a complete measurement system, including: silicon neural nanoprobe; flexi-cable that connects probe to headstage electronics; the headstage board itself, containing our custom 1024-channel ASIC; the back-end controller board with USB-3 output; first-gen graphical user interface software for controlling system and acquiring data (Mac and PC compatible). The ribbon cable picture between the headstage and the controller boards will, in practice, be replaced with a fine wire bundle to permit free behavior of the subject under study.

Figure 2. Headstage ASIC, Headstage Board, and Controller Board.

Figure 2. Headstage ASIC, Headstage Board, and Controller Board.

ASIC assembly to headstage

The headstage printed circuit board houses the custom 1,024-channel recording and stimulation ASIC, references voltages for sensitive analog circuits, bandpass filters, and line driver chips for driving the cable between the headstage and the subsequent data acquisition (DAQ) and control board. When received from the foundry, the custom 1,024-channel IC contains standard aluminum pads. The IC pads are subsequently solder-bumped to enable reliable and reproducible connections made between the die and the rest of the system.The protocol, as shown below in Figure 2. To connect the solder-bumped ASICs to the headstage, we simply apply solder flux, align the ASIC to the headstage, and follow with temperature reflow per conventional eutectic soldering procedures using a precision alignment/bondign system.

Figure 3.  Headstage Application Specific Integrated Circuit (ASIC) and bonding methodology. Given that our 1,024-channel ASIC die has lateral dimensions of only 6mm x 6mm, our next-gen headstage boards can be significantly reduced in size. This will facilitate their use with freely-behaving mice.

Figure 3.  Headstage Application Specific Integrated Circuit (ASIC) and bonding methodology. Given that our 1,024-channel ASIC die has lateral dimensions of only 6mm x 6mm, our next-gen headstage boards can be significantly reduced in size. This will facilitate their use with freely-behaving mice.

ASIC Performance

Our custom-designed ASIC enables full-bandwidth electrical recording & stimulation for up to 1,024 full-time channels. Critical design constraints are in minimizing die size for the large number of channels, while preserving bandwidth, noise performance, and low power dissipation per channel. The latter is particularly important for large-channel-count systems, as power dissipated in brain tissue must not lead to a temperature rise of greater than 0.1˚C to avoid perturbing activation thresholds. The data in Figure 3 below summarize the performance of our advanced ASICs. Also provided are comparisons with previous work; panels c shows that the ASIC provides far lower power dissipation per channel than similar, previously reported devices. Integrated noise for this ASIC in the 10Hz-10kHz range (for spike recordings) was 5.17μV rms, and in the DC-10kHz range (for LFP recordings) was 7.88μV rms. [Data used for comparison in panels c and d are obtained from: Dorman, et al. (1985); Ji and Wise (1992); Pancrazio et al. (1998); Harrison and Charles (2003); Sodagar et al. (2009); Gao et al. (2012); and Intan (2012).]

Figure 4.  Gen-2, Single-Chip, 1,024-Channel Multiplexing ASIC. a) Photograph of a die, with an inset (b) showing its array of electrical contact pads. c) Die area v. power dissipation for our 1,024-channel ASIC compared to reported performance of other bio-amplifiers. c) ASIC output induced by applying a 2.5mV sine wave to one channel, which was swept from 10Hz to 50kHz over 50ms. Frequency response is flat across the passband.

Figure 4.  Gen-2, Single-Chip, 1,024-Channel Multiplexing ASIC. a) Photograph of a die, with an inset (b) showing its array of electrical contact pads. c) Die area v. power dissipation for our 1,024-channel ASIC compared to reported performance of other bio-amplifiers. c) ASIC output induced by applying a 2.5mV sine wave to one channel, which was swept from 10Hz to 50kHz over 50ms. Frequency response is flat across the passband.

 

Software

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Coming soon...