Silicon Neural Nanoprobes
Quick Overview of Current Designs (Gen-2)
Here we provide a quick synopsis of the probe designs for the current generation of nanoprobes. Complete design documents for all nanoprobe foundry runs are provided at the bottom of this web page, under the heading "Design Documents".
These documents provide an overview of the production runs and elucidate design details for probe architectures that have been foundry fabricated en masse.
Current Generation (expected delivery ~Q4/2017):
Gen-2 (2016-2017) = Ephys & Echem (~12.6 MB)
Previous Generation(s) (not available for dissemination):
Gen-1 (2014-2015) = Ephys (~8.4 MB)
Reference: Rios et al., Nano Lett (2016)
Overview of Ephys / Echem Data Acquisition Architecture
Our Gen-2 Ephys / Echem data acquisition system is shown below in Figure 1. It is compatible with from one to four 256-channel probe layers (as described on our Probes web page) permitting assembly of instrumentation with either 256, 512, 768, or 1,024 full-time / full-bandwidth recording and stimulation channels. Each of our individual 256-channel probe layers are independently connected to the headstage via separate flexi-cables. These flexi-cables permit arbitrary and stress-free positioning of nanoprobes within the brain, untethered from the skull. They also permit experimentally-dependent scaling of probe-layer count, ranging from one to four probe layers in this generation. Our single-chip, custom 1,024-channel headstage ASIC (application specific integrated circuit) is mounted on the headstage board. The back end of the headstage board is connected by a cable to the controller board which provides system control signals, stimulation protocols, and enables streaming Ephys data to a PC through USB-3 connections. Data acquisition and system control software have been coded for both Linux OS and Mac OS X. These components are summarized in Figure 1 below.
ASIC assembly to headstage
The headstage printed circuit board houses the custom 1,024-channel recording and stimulation ASIC, references voltages for sensitive analog circuits, bandpass filters, and line driver chips for driving the cable between the headstage and the subsequent data acquisition (DAQ) and control board. When received from the foundry, the custom 1,024-channel IC contains standard aluminum pads. The IC pads are subsequently solder-bumped to enable reliable and reproducible connections made between the die and the rest of the system.The protocol, as shown below in Figure 2. To connect the solder-bumped ASICs to the headstage, we simply apply solder flux, align the ASIC to the headstage, and follow with temperature reflow per conventional eutectic soldering procedures using a precision alignment/bondign system.
Our custom-designed ASIC enables full-bandwidth electrical recording & stimulation for up to 1,024 full-time channels. Critical design constraints are in minimizing die size for the large number of channels, while preserving bandwidth, noise performance, and low power dissipation per channel. The latter is particularly important for large-channel-count systems, as power dissipated in brain tissue must not lead to a temperature rise of greater than 0.1˚C to avoid perturbing activation thresholds. The data in Figure 3 below summarize the performance of our advanced ASICs. Also provided are comparisons with previous work; panels c shows that the ASIC provides far lower power dissipation per channel than similar, previously reported devices. Integrated noise for this ASIC in the 10Hz-10kHz range (for spike recordings) was 5.17μV rms, and in the DC-10kHz range (for LFP recordings) was 7.88μV rms. [Data used for comparison in panels c and d are obtained from: Dorman, et al. (1985); Ji and Wise (1992); Pancrazio et al. (1998); Harrison and Charles (2003); Sodagar et al. (2009); Gao et al. (2012); and Intan (2012).]